The present invention relates to method and apparatus for converting analog signal into digital signal using an integrator.
When measured voltage is converted into digital output using well-known dual integration type analog-to-digital converter (hereinafter referred to as "A-D converter") an integrator including an integrating capacitor is first supplied with the measured voltage of one polarity only for a given period. Next, reference voltage having opposite polarity to the measured voltage is supplied until output voltage of the integrator returns to the initial value before supplying the measured voltage. Furthermore, the supply period of the reference voltage is measured by counting the clock pulses using a counter. As a result, digital output corresponding to the measured voltage can be obtained based on output of the counter. Accuracy of conversion using the dual integration type A-D converter is dependent on the measuring accuracy during the period supplying the reference voltage. In order to raise the conversion accuracy without decreasing the speed of analog-to-digital conversion, it is required that the repetition frequency of clock pulses is raised and that the time at which output voltage of the integrator returns to the initial value is detected with little time delay. However, it is difficult that such requirement be satisfied using dual integration type A-D converter.
Disadvantages in the above-mentioned dual integration type A-D converter can be eliminated by tripple integration type A-D converter such as disclosed in "HEWLETT-PACKARD JOURNAL" published on April 1981. The tripple integration type A-D converter changes level of the reference voltage. That is, when supply of the reference voltage is beginned and output voltage of the integrator approaches the initial value, level of the reference voltage is lowered. As a result, output voltage of the integrator slowly approaches the initial value. Thereby requirement of high speed for detecting the output voltage of the integrator returning to the initial value is relaxed.
However, when the initial value of output voltage of the integrator is detected, since variation of output voltage of the integrator with respect to one count of the counter, i.e. one period of clock pulse is quite small, initial value detecting capability of the detector must be raised. For example, when the measured voltage is 10 volt and output voltage of the integrator is 10 volt and it is assumed that analog-to-digital conversion is carried out at the resolution of 1/1,000,000, one count of the counter corresponds to 10 .mu.V therefore the detecting capability of 10 .mu.V is required to detect the initial value.
If maximum output, i.e. output amplitude of the integrator is enlarged when the measured voltage is integrated, detection of the initial value is made easy. However, in view of voltage-resistant property of the integrator and the power source capacity, maximum output voltage cannot be raised without limitation.